`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:42:41 11/21/2013
// Design Name:   Level_decode_onetime
// Module Name:   G:/Xilinx_Proj/H_264_test/Level_decode_onetime_test.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Level_decode_onetime
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Level_decode_onetime_test;

	// Inputs
	reg [3:0] Level_prefix;
	reg [15:0] Level_suffix;
	reg [2:0] SuffixLength;
	// Outputs
	wire [15:0] Level_abs;
	wire Level_sign;
	reg clk,rst;
	reg [8:0] cnt;
	// Instantiate the Unit Under Test (UUT)
	Level_decode_onetime uut (
		.Level_prefix(Level_prefix), 
		.Level_suffix(Level_suffix), 
		.SuffixLength(SuffixLength), 
		.Level_abs(Level_abs), 
		.Level_sign(Level_sign)
	);

	initial begin
		// Initialize Inputs
		Level_prefix = 0;
		Level_suffix = 0;
		SuffixLength = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
	#100 rst=1; 
		 #100 rst=0; 
		 #100 rst=1; 
		 clk=0;
		 cnt=0;
	end
      
always begin #50 clk=~clk; end
  
always @(negedge rst or posedge clk) begin
		if(!rst) begin
			cnt<=0;
		end
		else begin
			case(cnt)
			0:begin
				Level_prefix<=3; Level_suffix<=0; SuffixLength<=0;cnt<=cnt+1'b1;
			end
			1:begin
				Level_prefix<=2; Level_suffix<=0; SuffixLength<=1;cnt<=cnt+1'b1;
			end
			2:begin
				Level_prefix<=3; Level_suffix<=0; SuffixLength<=1;cnt<=cnt+1'b1;
			end
			3:begin
				Level_prefix<=0; Level_suffix<=2'b11; SuffixLength<=2;cnt<=cnt+1'b1;
			end
			4:begin
				Level_prefix<=0; Level_suffix<=0; SuffixLength<=0;cnt<=cnt+1'b1;
			end
			5:begin
				Level_prefix<=2; Level_suffix<=0; SuffixLength<=1;cnt<=cnt+1'b1;
			end
			6:begin
				Level_prefix<=4; Level_suffix<=0; SuffixLength<=1;cnt<=cnt+1'b1;
			end
			default:begin
				cnt<=0;
			end
			endcase
		end
end					
		
endmodule

